(1) FIELD OF THE INVENTION
This invention relates to an integrated circuit semiconductor device, and more particularly, to a method for fabricating dynamic random access memory (DRAM) having DRAM cells with fork-shaped stacked capacitors for increased capacitance.
(2) DESCRIPTION OF THE PRIOR ART
In recent years there has been a dramatic increase in the integrated circuit density on the semiconductor substrate and the semiconductor chips formed therefrom. This increase in density has resulted from the down sizing of the individual devices and the resulting increase in device packing density. The reduction in device size was achieved predominantly by recent advances in high resolution photolithography, directional (anisotropic) plasma etching and other semiconductor technology innovations. However, future requirements for even greater circuit density is putting additional demand on the semiconductor processing technologies and also on the device electrical requirements.
The DRAM chip used in the electronics industry for storing information is one of the circuit types experiencing this demand for increased density. The circuit on the DRAM chip consists in part of an array of individual DRAM storage cells that store binary data (bits) as electrical charge on a storage capacitor. This information is stored or retrieved from the storage capacitor by means of a pass transistor on each memory cell, and by address and read/write circuits on the periphery of the DRAM chip. The pass transistor is usually a field-effect-transistor (FET) and the single capacitor in each cell is either formed in the semiconductor substrate as a trench capacitor or built over the FET in the cell area as a stacked capacitor. By the year 1998 the number of memory cells (bits) on a DRAM chip are expected to reach about 256 million and by the year 2001 the bit count on the DRAM chip is expect to reach about 1 Gigabits.
With this rapid increase in the number of memory cells on the DRAM chip, and the need to maintain a reasonable chip size with improved circuit performance, the area of the individual cells must be further reduced in size. As the cell size decreases it becomes more difficult to fabricate a stacked capacitor with sufficient capacitance to store the necessary charge to provide an acceptable signal-to-noise level for the read circuit (sense amplifiers) to detect. The reduced charge also necessitates increasing the refresh cycle frequency that periodically restores the charge on these volatile storage cells. Since the capacitor area is limited to the cell size in order to accommodate the multitude of cells on the DRAM chip, it is necessary to explore alternative methods for increasing the capacitance without increasing the lateral area that the capacitor occupies on the substrate surface.
Many three-dimensional stacked storage capacitor structures have been reported in the literature for increasing the capacitance, but generally require additional processing steps that including optical alignment and exposure for photoresist masks. For example, C. Koh in U.S. Pat. No. 5,364,813, teaches a method of forming a fin-shaped like capacitor. The method includes depositing a polysilicon layer on the substrate having a sacrificial borophosphosilicate glass (BPSG) in which the capacitor node contact openings are etched. The bottom capacitor electrodes are then formed by patterning the polysilicon layer using a photoresist mask aligned to the contact. Another capacitor structure is reported by Y. Park et al, U.S. Pat. No. 5,332,685 in which the bit line and storage node contacts are formed by simultaneously forming polysilicon plugs. The bit lines are then formed from a polysilicon or polycide layer by aligning a photoresist mask and patterning the polysilicon layer. Fork-shaped bottom electrodes are then formed over the storage node contacts adjacent to the bit lines which restricts the size of the electrode. Still another fork-shaped electrode type capacitor is reported by J. Ahn, U.S. Pat. No. in which the bottom electrode of the capacitor is aligned over a conducting plug in the node contact.
As the DRAM cell continues to decrease in size it becomes increasing more important to reduce the number of mask alignment steps to minimize the ground rule tolerance and improve the cell density. Therefore, there is still a strong need in the semiconductor industry for making a reliable low cost DRAM product using improved processing steps.